A static random-access memory (SRAM) device is a type of semiconductor memory that uses bistable latching circuitry to store each data bit. SRAM devices, in contrast with dynamic random-access memory (DRAM) devices, have the ability to maintain the stored data without needing the data to be periodically refreshed. A memory cell in a conventional SRAM device is shown in FIG. 1. Referring to FIG. 1, the single SRAM cell may comprise first and second driving transistors TN1 and TN2, first and second load transistors TP1 and TP2, and first and second access transistors TN3 and TN4. Source terminals of the first and second driving transistors TN1 and TN2 may be connected to a ground voltage line Vss, and source terminals of the first and second load transistors TP1 and TP2 may be connected to a power voltage line Vdd.
The first driving transistor TN1 comprising an NMOS transistor and the first load transistor TP1 comprising a PMOS transistor may be configured as a first inverter, and the second driving transistor TN2 comprising an NMOS transistor and the second load transistor TP2 comprising a PMOS transistor may be configured as a second inverter.
Output terminals of the first and second inverters may be connected to source terminals of the first and second access transistors TN3 and TN4. In addition, input and output terminals of the first and second inverters may intersect with each other and be connected to each other. Drain terminals of the first and second access transistors TN3 and TN4 may be connected to first and second bit lines BL and /BL, respectively.
As shown in FIG. 1, a single SRAM memory cell may comprise six transistors, which may consume significant SRAM layout real estate in integrated circuit memory devices as SRAM device density increases.